Features for the AM3354
| Parameter | Feature Description |
|---|---|
| Processor | 1-GHz Sitara™ ARM Cortex®-A8, 32-bit RISC processor |
| NEON™ SIMD Coprocessor | Supports SIMD for multimedia processing |
| L1 Cache | 32KB instruction and 32KB data cache with single-error detection (Parity) |
| L2 Cache | 256KB cache with Error-Correcting Code (ECC) |
| Boot ROM | 176KB on-chip boot ROM |
| RAM | 64KB dedicated RAM |
| External Memory Support | mDDR, DDR2, DDR3, DDR3L with 16-bit data bus and up to 1GB addressable space |
| General-Purpose Memory Controller (GPMC) | Supports NAND, NOR, Muxed-NOR, SRAM with BCH and Hamming ECC support |
| PRU-ICSS | Real-time industrial communication subsystem with two PRUs supporting EtherCAT, PROFIBUS, PROFINET, EtherNet/IP |
| Interrupt Controller | Supports up to 128 interrupt requests |
| Power Management | SmartReflex™ adaptive voltage scaling and Dynamic Voltage Frequency Scaling (DVFS) |
| Debugging | JTAG and boundary scan for debugging and system inspection |
| DMA | 64 channels, 8 QDMA channels, inter-processor communication support |
| Security | AES, SHA, RNG hardware accelerators, optional secure boot |
| USB Ports | Up to 2 USB 2.0 high-speed DRD ports with integrated PHY |
| Ethernet MACs | Up to 2 industrial gigabit Ethernet MACs, IEEE 1588v1 Precision Time Protocol (PTP) |
| CAN Ports | Up to 2 Controller-Area Network (CAN) ports |
| Audio Ports | Up to 2 McASP multichannel audio serial ports with TDM, I2S, and SPDIF support |
| Graphics Engine | SGX530 3D graphics engine with up to 20 million polygons/sec and support for Direct3D, OGL-ES |
| LCD Controller | Supports up to 2048x2048 resolution, integrated raster controller with DMA engine |
| ADC | 12-bit SAR ADC with 200K samples/sec and configurable touch screen controller |
| PWM Modules | Up to 3 enhanced high-resolution PWM modules with time and frequency control |
| eQEP Modules | Up to 3 enhanced quadrature encoder pulse (eQEP) modules for position feedback |
| Package Options | 298-pin S-PBGA-N298 and 324-pin S-PBGA-N324 packages with 0.65mm and 0.80mm ball pitch |
Description for the AM3354
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing,
peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS).
Processor SDK Linux® and TI-RTOS are available free of charge from TI.The AM335x microprocessor contains the subsystems shown
in the Functional Block Diagram and a brief description of each follows:The contains the subsystems shown in the Functional Block
Diagram and a brief description of each follows:The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor
and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility.
The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS,
Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and
all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations,
custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.