| Category | Parameter | Specification |
|---|---|---|
| Processor | Main CPU | 1 GHz ARM Cortex-A8 32-bit RISC + NEON SIMD |
| Real-Time Units | Dual PRU-ICSS (200 MHz, 32-bit each) | |
| Cache / Memory | L1 Cache | 32 KB I-Cache + 32 KB D-Cache (parity) |
| L2 Cache | 256 KB (ECC) | |
| On-Chip RAM | 64 KB Dedicated RAM + 64 KB OCMC RAM + 176 KB Boot ROM | |
| External Memory | 16-bit DDR2/3/3L/mDDR, up to 1 GB addressable | |
| Display / Graphics | LCD Controller | Up to 2048×2048@24 bpp, integrated LIDD & Raster engines |
| GPU | SGX530, 20 Mpoly/s, OpenGL ES 1.1/2.0 | |
| Touch Support | 12-bit SAR ADC, 4-/5-/8-wire resistive TSC | |
| Connectivity | Ethernet | 2× 10/100/1000 Mbps MACs with integrated switch, IEEE 1588 PTP |
| USB | 2× USB 2.0 HS DRD ports with integrated PHY | |
| Serial | 6× UARTs (up to 12 Mbps), 2× CAN (2.0A/B) | |
| Storage | 3× MMC/SD/SDIO interfaces (up to 48 MHz) | |
| Industrial Protocols | EtherCAT, PROFINET, EtherNet/IP, etc. via PRU-ICSS | |
| Timing / Control | PWM | 3× eHRPWM modules (6 outputs) |
| Encoder / Capture | 3× eQEP + 3× eCAP modules | |
| System Management | Clock / Power | DVFS, SmartReflex™ adaptive voltage scaling |
| RTC | Independently powered with alarm/wake-up | |
| Security | AES, SHA, RNG accelerators; optional secure boot | |
| Packages | 298-pin | S-PBGA-N298, 0.65 mm pitch (ZCE) |
| 324-pin | S-PBGA-N324, 0.80 mm pitch (ZCZ) |
Description for the AM3352
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing,
peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS).
Processor SDK Linux® and TI-RTOS are available free of charge from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator
subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility.
The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS,
Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins,
events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses,
specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.