AM3352BZCZA80

TEXAS INSTRUMENTS

Sitara processor: Arm Cortex-A8, 1Gb Ethernet, display, CAN


Download Specifications

Features for the AM3352

CategorySpecification
Processor CoreUp to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor with NEON™ SIMD Coprocessor
Cache Memory
  • L1: 32KB Instruction + 32KB Data Cache with Parity
  • L2: 256KB Cache with ECC
Memory Interfaces
  • EMIF: Supports mDDR, DDR2, DDR3, DDR3L (up to 800MHz data rate)
  • GPMC: 8/16-bit async interface with ECC support
PRU-ICSS
  • Two 200MHz Programmable Real-Time Units
  • Supports Industrial Protocols (EtherCAT®, PROFIBUS, etc.)


Description for the AM3352

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, 

peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). 

Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics 

Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. 

The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, 

Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, 

events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling

 operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.