Features for the AM3352
| Module | Key Specifications |
|---|---|
| Processor | Sitara™ ARM® Cortex®-A8 up to 1 GHz NEON™ SIMD coprocessor |
| Cache | L1: 32 KB I-Cache + 32 KB D-Cache (parity) L2: 256 KB (ECC) |
| On-Chip Memory | Boot ROM: 176 KB Dedicated RAM: 64 KB OCMC RAM: 64 KB (retention-capable) |
| External Memory IF | EMIF: 16-bit mDDR/DDR2/DDR3/DDR3L, up to 1 GB address space GPMC: 8-/16-bit NAND/NOR/SRAM, 7 chip selects, BCH/Hamming ECC |
| PRU-ICSS | 2×PRU RISC @200 MHz, 8 KB I-RAM + 8 KB D-RAM each 12 KB shared RAM, industrial protocols (EtherCAT, PROFINET, etc.) 2×MII Ethernet, 1×UART, 1×eCAP, 1×MDIO |
| Clock & Power | 15–35 MHz on-chip osc, 5 ADPLLs SmartReflex™ AVS + DVFS, 3 switchable power domains |
| RTC | Independent 32.768 kHz osc, alarm wake-up, dedicated power |
| USB | 2×USB 2.0 High-Speed DRD (integrated PHY) |
| Ethernet | 2×Industrial Gigabit MAC (10/100/1000 Mbps) Integrated switch, IEEE 1588v1 PTP, MII/RMII/RGMII |
| CAN | 2×CAN 2.0B ports |
| McASP | 2×McASP, 4 serial data pins each, 50 MHz clocks I²S/TDM/SPDIF/AES-3, 256 B FIFO |
| UART | 6×UART (all IrDA/CIR, RTS/CTS; UART1 full modem) |
| SPI | 2×McSPI (master/slave, 48 MHz, 2 chip selects) |
| MMC/SD/SDIO | 3×MMC/SD/SDIO (1-/4-/8-bit, 48 MHz, MMC4.3/SD2.0) |
| I²C | 3×I²C (standard 100 kHz / fast 400 kHz) |
| GPIO | 4 banks × 32 GPIO (128 total), 2 interrupts per bank |
| Timers | 8×32-bit general-purpose timers (DMTIMER1 1-ms tick) 1×watchdog |
| 3D Graphics | SGX530: 20 M polygons/s, OpenGL ES 1.1/2.0, Direct3D Mobile |
| LCD Controller | Up to 2048×2048 @126 MHz, 24-bit RGB, 512-word DMA FIFO |
| ADC | 12-bit SAR ADC, 200 kS/s, 8 channels 4-/5-/8-wire resistive touch controller |
| PWM | 3×eHRPWM (6 single-ended / 3 differential), 3×eCAP (configurable PWM) |
| QEP | 3×32-bit eQEP modules |
| DMA | EDMA: 64 logical + 8 QDMA channels, 3 TPTC + 1 TPCC |
| Security | AES, SHA, RNG accelerators; optional secure boot |
| Debug | JTAG, cJTAG, IEEE 1500, boundary scan |
| Packages | 298-Pin S-PBGA-N298 (ZCE, 0.65 mm) 324-Pin S-PBGA-N324 (ZCZ, 0.80 mm) |
Description for the AM3352
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing,
peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS).
Processor SDK Linux® and TI-RTOS are available free of charge from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator
subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility.
The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS,
Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events
and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations,
custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.